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1 automotive single supply, spdt analog switch ISL76123 the intersil ISL76123 device is a small precision, bidirectional, single-pole/double throw (spdt) analog switch, designed to operate from a single +2.7v to +12v supply. the device is supplied in a 6 ld sot-23 package. targeted applications include automotive battery powered systems that can benefit from the device?s low power consumption (5w), low leakage currents (3na max), and fast switching speeds (t on = 28ns, t off = 20ns). this device will often find use in infotainment systems to ?mux - in? additional functions to gpio pins on socs. the device ensures the switching function is always break-before-make to help eliminate transient signal problems. its small package size alleviates board space limitations. the part has been qualified for use in automotive applications over an operating temperature range of -40c to +105c. features ? fully specified at 12v, 5v, and 3.3v supplies for 10% tolerances ? on-resistance (r on ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ? ?r on matching between channels . . . . . . . . . . . . . . . . . . . . . . . <1 ? ? low charge injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pc (max) ? single supply operation . . . . . . . . . . . . . . . . . . . . . . +2.7v to +12v ? low power consumption (p d ) . . . . . . . . . . . . . . . . . . . . . . . . <5w ? low leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10na ? fast switching action -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns ? guaranteed break-before-make switching ? minimum 2000v esd protection ?ttl, cmos compatible ? available in 6 ld sot-23 package ? pb-free (rohs compliant) ? aec-q100 qualified applications ? audio and video switching ? general signal ?mux - in? (where gpio lines may be constrained) ? various building block control applications -filters - signal conditioning - integration reset circuits table 1. features at a glance ISL76123 sw 1/sw 2 spdt or 2x1 mux 3.3v r on 42 ? 3.3v t on /t off 40ns/20ns 5v r on 23 ? 5v t on /t off 28ns/20ns 12v r on 15 ? 12v t on /t off 25ns/17ns package 6 ld sot-23 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. september 28, 2012 fn8297.1
ISL76123 2 fn8297.1 september 28, 2012 pin configuration (note) ISL76123 (6 ld sot-23) top view note: switch shown for logic ?0? input. 4 5 6 1 2 3 in v+ gnd no nc com truth table logic ISL76123 pin nc pin no 0onoff 1offon note: logic ?0? 0.8v. logic ?1? 2.4v. pin descriptions pin name pin number function v+ 2 system power supply input (+2.7v to +12v) gnd 3 ground connection in 1 digital control input com 5 analog switch common pin no 6 analog switch normally open pin nc 4 analog switch normally closed pin ordering information part number (notes 1, 2, 3) part marking (note 4) temp. range (c) package (pb-free) pkg. dwg. # ISL76123ahz-t 123a -40 to +105 6 ld sot-23 tape and reel p6.064 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-fr ee products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL76123 . for more information on msl please see tech brief tb363 . 4. the part marking is located on the bottom of the part.
ISL76123 3 fn8297.1 september 28, 2012 absolute maximum rating s thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15v input voltages in (note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((v+) + 0.3v) no, nc (note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((v+) + 0.3v) output voltages com (note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((v+) + 0.3v) continuous current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . . . . . . . . 40ma esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 100v charged device model (tested per jesd22-c101). . . . . . . . . . . . . . . 1kv latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 6 ld sot-23 package (notes 6, 7) . . . . . . . 175 95 maximum junction temperature (plastic package) . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. signals on nc, no, com, or in exceeding v+ or gnd are clamped by internal diodes. limit forward diode current to maximum curr ent ratings. 6. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is taken at the package top center. electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +105c. parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 4.5v, i com = 1.0ma, v no or v nc = 3.5v (figure 5) +25 - 23 34 ? full - 25 40 ? r on matching between channels, r on v+ = 5v, i com = 1.0ma, v no or v nc = 3.5v +25 - 0.8 2 ? full - 1 4 ? r on flatness, r flat(on) v+ = 5v, i com = 1.0ma, v no or v nc = 1v, 2v, 3v (note 11) full - 7 8 ? no or nc off leakage current, i no(off) or i nc(off) v+ = 5.5v, v com = 1v, 4.5v, v no or v nc = 4.5v, 1v +25 -3 0.01 3 na full -5 - 5 na com off leakage current, i com(off) v+ = 5.5v, v com = 4.5v, 1v, v no or v nc = 1v, 4.5v +25 -3 - 3 na full -5 - 5 na com on leakage current, i com(on) v + = 5.5v, v com = 1v, 4.5v, or v no or v nc = 1v, 4.5v or floating +25 -5 - 5 na full -10 - 10 na dynamic characteristics turn-on time, t on v no or v nc = 3v, r l = 1k ? , c l = 35pf, v in =0vto3v (see figure 1) +25 - 28 - ns full - 40 - ns turn-off time, t off v no or v nc = 3v, r l = 1k ? , c l = 35pf, v in =0vto3v (see figure 1) +25 - 20 - ns full - 30 - ns break-before-make time delay, t d r l = 300 ? , c l = 35pf, v no = v nc = 3v, v in =0vto3v (see figure 3) full - 10 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ? (see figure 2) +25 - 3 - pc off isolation r l = 50 ? , c l = 5pf, f = 1mhz (see figure 4) +25 - 76 - db power supply rejection ratio r l = 50 ? , c l = 5pf, f = 1mhz +25 - 60 - db no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) +25 - 8 - pf
ISL76123 4 fn8297.1 september 28, 2012 com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v (see figure 7) +25 - 8 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) +25 - 28 - pf power supply characteristics power supply range full 2.7 - 12 v positive supply current, i+ v+ = 5.5v, v in = 0v or v+, all channels on or off full -1 0.0001 1 a digital input characteristics input voltage low, v inl full - - 0.8 v input voltage high, v inh full 2.4 --v input current, i inh , i inl v+ = 5.5v, v in = 0v or v+ full -1 - 1 a electrical specifications - 3.3v supply test conditions: v+ = +3.0v to +3.6v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +105c. parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 3v, i com = 1.0ma, v no or v nc = 1.5v +25 - 42 60 ? full - 45 70 ? r on matching between channels, r on v+ = 3.3v, i com = 1.0ma, v no or v nc = 1.5v +25 - 0.8 2 ? full - 1 4 ? r on flatness, r flat(on) v+ = 3.3v, i com = 1.0ma, v no or v nc = 0.5v, 1v, 1.5v +25 - 6 10 ? full - 7 12 ? no or nc off leakage current, i no(off) or i nc(off) v+ = 3.6v, v com = 1v, 3v, v no or v nc = 3v, 1v +25 -3 0.01 3 na full -5 - 5 na com off leakage current, i com(off) v+ = 3.6v, v com = 3v, 1v, v no or v nc = 1v, 3v +25 -3 0.01 3 na full -5 - 5 na com on leakage current, i com(on) v + = 3.6v, v com = 1v, 3v, or v no or v nc = 1v, 3v or floating +25 -5 - 5 na full -10 - 10 na dynamic characteristics turn-on time, t on v no or v nc = 1.5v, r l = 1k ? , c l = 35pf, v in = 0v to 3v +25 - 40 - ns full - 60 - ns turn-off time, t off v no or v nc = 1.5v, r l = 1k ? , c l = 35pf, v in = 0v to 3v +25 - 20 - ns full - 30 - ns break-before-make time delay, t d r l = 300 ? , c l = 35pf, v no or v nc = 1.5v, v in = 0v to 3v full - 20 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ? +25 - 1 - pc off isolation r l = 50 ? , c l = 5pf, f = 1mhz +25 - 76 - db power supply rejection ratio r l = 50 ? , c l = 5pf, f = 1mhz +25 - 56 - db no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v +25 - 8 - pf com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v +25 - 8 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (figure 7) +25 - 28 - pf electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating te mperature range, -40c to +105c. (continued) parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units
ISL76123 5 fn8297.1 september 28, 2012 power supply characteristics positive supply current, i+ v+ = 3.6v, v in = 0v or v+, all channels on or off full -1 - 1 a digital input characteristics input voltage low, v inl full - - 0.8 v input voltage high, v inh full 2.4 -- v input current, i inh , i inl v+ = 3.6v, v in = 0v or v+ full -1 - 1 a electrical specifications - 12v supply test conditions: v+ = +10.8v to +13v, gnd = 0v, v inh = 4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +105c. parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 10.8v, i com = 1.0ma, v no or v nc = 10v +25 - 15 23 ? full - 16 25 ? r on matching between channels, r on v+ = 12v, i com = 1.0ma, v no or v nc = 10v +25 - 0.8 2 ? full - 1 4 ? r on flatness, r flat(on) v+ = 12v, i com = 1.0ma, v no or v nc = 3v, 6v, 9v (note 11) +25 - 1 4 ? full - - 6 ? no or nc off leakage current, i no(off) or i nc(off) v+ = 13v, v com = 1v, 12v, v no or v nc = 12v, 1v +25 -3 0.01 3 na full -5 - 5 na com off leakage current, i com(off) v+ = 13v, v com = 12v, 1v, v no or v nc = 1v, 12v +25 -3 0.01 3 na full -5 - 5 na com on leakage current, i com(on) v + = 13v, v com = 1v, 12v, or v no or v nc = 1v, 12v or floating +25 -5 - 5 na full -12 - 12 na dynamic characteristics turn-on time, t on v no or v nc = 10v, r l = 1k ? , c l = 35pf, v in = 0v to 4v +25 - 25 - ns full - 35 - ns turn-off time, t off v no or v nc = 10v, r l = 1k ? , c l = 35pf, v in = 0v to 4v +25 - 17 - ns full - 26 - ns break-before-make time delay, t d r l = 300 ? , c l = 35pf, v no or v nc = 10v, v in = 0v to 4v full - 2 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ? +25 - 5 - pc off isolation r l = 50 ? , c l = 5pf, f = 1mhz +25 - 76 - db crosstalk (channel-to-channel) r l = 50 ? , c l = 5pf, f = 1mhz +25 - -105 - db power supply rejection ratio r l = 50 ? , c l = 5pf, f = 1mhz +25 - 63 - db no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v +25 - 8 - pf com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v +25 - 8 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (figure 7) +25 - 28 - pf power supply characteristics positive supply current, i+ v+ = 13v, v in = 0v or v+, all channels on or off full -1 - 1 a electrical specifications - 3.3v supply test conditions: v+ = +3.0v to +3.6v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temp erature range, -40c to +105c. (continued) parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units
ISL76123 6 fn8297.1 september 28, 2012 digital input characteristics input voltage low, v inl full - - 0.8 v input voltage high, v inh full 4 -- v input current, i inh , i inl v+ = 13v, v in = 0v or v+ full -1 - 1 a notes: 8. v in = input voltage to perform proper function. 9. the algebraic convention, whereby the most negative value is a mi nimum and the most positive a ma ximum, is used in this data sheet. 10. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11. limits established by characteriza tion and are not production tested. test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement points figure 2b. test circuit figure 2. charge injection electrical specifications - 12v supply test conditions: v+ = +10.8v to +13v, gnd = 0v, v inh = 4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temp erature range, -40c to +105c. (continued) parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units 50% t r < 20ns t f < 20ns t off 90% 3v or 4v 0v v no 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on + ----------------------- - = switch input logic input v out r l c l com no or nc in 1k ? 35pf gnd v+ c v out v out on off on q = v out x c l switch output logic input v+ 0v c l v out r g v g gnd com no or nc v+ c logic input in
ISL76123 7 fn8297.1 september 28, 2012 figure 3a. measurement points c l includes fixture and stray capacitance. figure 3b. test circuit figure 3. break-before-make time figure 4. off isolation test circuit figure 5. r on test circuit figure 6. crosstalk test circuit figure 7. capacitance test circuit test circuits and waveforms (continued) 90% 3v or 4v 0v t d logic input switch output 0v v out logic input in com r l c l v out 35pf 300 ? no nc v+ gnd v nx c analyzer r l signal generator v+ c 0v or v inh no or nc com in x gnd v+ c 0.8v or v inh no or nc com in gnd v nx v 1 r on = v 1 /1ma 1ma 0v or 2.4v analyzer v+ c no1 or nc1 signal generator r l gnd in 1 com1 in 2 50 ? 0v or v inh nc com2 no2 or nc2 v+ c gnd no or nc com in x impedance analyzer 0v or v inh
ISL76123 8 fn8297.1 september 28, 2012 detailed description the ISL76123 bidirectional, single spdt analog switch offers precise switching capability from a single 2.7v to 12v supply with low on-resistance (23 ? ) and high speed operation (t on = 28ns, t off = 20ns). the device is especially well suited to automotive battery powered systems thanks to the low operating supply voltage (2.7v), low power consumption (5w), low leakage currents (3na max), and the tiny sot-23 packaging. high frequency applications also benefi t from the wide bandwidth, and the very high off isolation rejection. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and gnd (see figure 8). to prevent forward biasing these diodes, v+ must be applied before any input signals, and inpu t signal voltages must remain between v+ and gnd. if these conditions cannot be guaranteed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k ? resistor in series with the input (see figure 8). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. adding a series resistor to the switch input defeats the purpose of using a low r on switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see figure 8). these additional diodes limit the analog signal from 1v below v+ to 1v abov e gnd. the low leakage current performance is unaffected by this approach, but the switch resistance may increase, especi ally at low supply voltages. power-supply considerations the ISL76123 construction is typical of most cmos analog switches, except that they have only two supply pins: v+ and gnd. v+ and gnd drive the internal cmos switches and set their analog voltage limits. unlike switches with a 13v maximum supply voltage, the ISL76123 15v maximum supply voltage provides plenty of room for the 10% tolerance of 12v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 2.7v. it is important to note that the input signal range, switching times, and on-resistance degrade at lowe r supply voltages. refer to the ?electrical specification? tables beginning on page 3 and ?typical performance curves? beginning on page 9 for details. v+ and gnd also power the intern al logic and level shifter. the level shifter convert the input logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. this device cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. logic-level thresholds this switch is ttl compatible (0.8v and 2.4v) over a supply range of 3v to 11v (see figure 15). at 12v the v ih level is about 2.5v. this is still below the ttl guaranteed high output minimum level of 2.8v, but noise margin is reduced. for best results with a 12v supply, use a logic family the provides a v oh greater than 3v. the digital input stages draw su pply current whenever the digital input voltage is not at one of th e supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 ? systems, signal response is reasonably flat even past 300mhz (see figure 16 ). figure 16 also illustrates that the frequency response is very consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to its output. off isolation is the resistance to this feedthrough. figure 17 details the high off isolation rejection provided by this part. at 10mhz, off isolation is about 50db in 50 ? systems, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off isolation rejection due to the voltage divider action of the switch off impedanc e and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leakag e current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means th eir leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pins constitutes the anal og-signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage currents of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. figure 8. overvoltage protection gnd v com v no or nc optional protection v+ in x diode optional protection diode optional protection resistor
ISL76123 9 fn8297.1 september 28, 2012 typical performance curves t a = +25c, unless otherwise specified. figure 9. on-resistance vs supply voltage f igure 10. on-resistance vs switch voltage figure 11. r on match vs switch voltage figure 12. charge injection vs switch voltage figure 13. turn-on time vs supply voltage figure 14. turn-off time vs supply voltage r on ( ? ) v+ (v) 35 25 15 5 345678910111213 +25c -40c +85c 10 20 30 40 r on ( ? ) v com (v) 15 5 0 4 6 8 10 12 10 20 2 20 15 25 10 25 20 30 15 40 45 v+ = 3.3v v+ = 5v v+ = 12v +25c -40c +85c +25c -40c +85c +25c -40c +85c 30 35 -40c dr on ( ? ) v com (v) 0.10 0 0 4 6 8 10 12 0.05 0.15 2 v+ = 3.3v v+ = 5v v+ = 12v +25c -40c +85c 0.10 0.05 0.15 0 0.20 0.25 +25c -40c +85c 0.20 0.10 0.30 0 0.40 0.50 +25c -40c +85c +85c +25c q (pc) v com (v) 60 40 20 0 -20 0 4681012 -10 10 30 50 v+ = 3.3v 2 v+ = 5v v+ = 12v t on (ns) v+ (v) 100 80 60 40 20 23456789101112 30 50 70 90 -40c +25c +85c t off (ns) v+ (v) 35 30 25 20 15 23456789101112 +25c -40c +85c -40c
ISL76123 10 fn8297.1 september 28, 2012 figure 15. digital switching point vs su pply voltage figure 16 . frequency response figure 17. off isolation figure 18. psrr vs frequency typical performance curves t a = +25c, unless otherwise specified. (continued) v+ (v) 25 3.0 2.5 2.0 1.5 1.0 0.5 34 678910111213 v inh and v inl (v) -40c +85c +25c -40c +85c v inh v inl +85c +25c frequency (mhz) 0 -3 -6 normalized gain (db) gain phase v+ = 3.3v to 12v 0 20 40 60 80 100 phase () 1 10 100 600 v in = 0.2v p-p to 2.5v p-p (v+ = 3.3v) v in = 0.2v p-p to 4v p-p (v+ = 5v) v in = 0.2v p-p to 5v p-p (v+ = 12v) r l = 50 ? frequency (hz) 1k 100k 1m 100m 500m 10k 10m off isolation (db) 110 10 20 30 40 50 60 70 80 90 100 isolation v+ = 3v to 13v frequency (mhz) 1 10 100 1000 0.3 30 40 50 psrr (db) 60 70 80 20 10 0 r l = 50 ? v+ = 12v, switch on v+ = 3.3v, switch on v+ = 3.3v, switch off v+ = 12v, switch off
ISL76123 11 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8297.1 september 28, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL76123 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change september 28, 2012 fn8297.1 initial release.
ISL76123 12 fn8297.1 september 28, 2012 package outline drawing p6.064 6 lead small outline transistor plastic package rev 4, 2/10 dimension is exclusive of mold flash, protrusions or gate burrs. package conforms to jedec mo-178ab. foot length is measured at reference to gauge plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 5. 3. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view end view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.10 2.90 0.10 0.95 1.60 +0.15/-0.10 2.80 0.00-0.15 1.15 +0.15/-0.25 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 0.08-0.22 see detail x (0.25) 1.45 max (0.60) 0-8 c b a d 3 3 3 3 0.20 c 2x 123 654 plane

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